Qsys Builder of Altera QuartusII 10.1

I try to use qsys to rebuild my verification system that is shown as follow.

In qsys, some components are different form sopc builder. The Nor Flash(CFI) controller was replaced by Generic Tristate Controller. The altpll component doesn`t directly output clock, and the clock bridge component uses to output the clock of the sdram. The interface of the component can configure to directly export to outside of qsys.

Qsys has a new AvalonMM component is Avalon-MM Crossing Clock component. It uses the dual channel fifo to separate the different clock. In this case, I try to use it to replace the bus bridge 0, but the timingquest doesn`t met. I don`t understand what`s happen? The SDC file is generated by qsys. It means the design constrain is control by qsys. So, the bus bridge still use the Avalon-MM pipeline bridge.

This verification system uses the qsys to generate that can operate at 176Mhz in the DE2-115(Cyclone-IV).

FX2LP Slave FIFO Mode (cy7c68013a)

FX2LP Slave FIFO Mode Firmware

The 8051 of the FX2LP only uses to initial the configuration register, and the configuration of the endpoint is shown as follow:


EP2 OUT
4x Buffer
512 Bytes Packet
Auto-OUT

EP6 IN
4x Buffer
512 Bytes Packet
Auto-IN

void TD_Init( void )
{ 
    CPUCS = 0x12;                       // cpu freq. = 24Mhz
    SYNCDELAY; 
 
    IFCONFIG = 0xA3;                    // ifclk freq. = 30Mhz
    SYNCDELAY;

    PINFLAGSAB = 0x88;   // FLAGA - EP2 EF
    SYNCDELAY;
    PINFLAGSCD = 0xEE;   // FLAGD - EP6 FF
    SYNCDELAY;

    PORTACFG |= 0x80;
    SYNCDELAY;

    FIFOPINPOLAR = 0x3F;                // setting all interface to high active
    SYNCDELAY;
      
    EP4CFG = 0x02; // Clear Valid                    
    SYNCDELAY;
    EP8CFG = 0x02; // Clear Valid
    SYNCDELAY;                   
    EP2CFG = 0xA0;// OUT 512 4x
    SYNCDELAY;
    EP6CFG = 0xE0;// IN  512 4x
    SYNCDELAY;
     
    // Clear FIFO
    FIFORESET = 0x80;             // activate NAK-ALL to avoid race conditions
    SYNCDELAY;                    
    FIFORESET = 0x02;             // reset, FIFO 2
    SYNCDELAY;                    // 
    FIFORESET = 0x04;             // reset, FIFO 4
    SYNCDELAY;                    // 
    FIFORESET = 0x06;             // reset, FIFO 6
    SYNCDELAY;                    // 
    FIFORESET = 0x08;             // reset, FIFO 8
    SYNCDELAY;                    // 
    FIFORESET = 0x00;             // deactivate NAK-ALL
    SYNCDELAY;

    // OUT EP2
    EP2FIFOCFG = 0x01; // AUTOOUT = 0             
    SYNCDELAY;
    OUTPKTEND = 0x82; // 1x
    SYNCDELAY;
    OUTPKTEND = 0x82; // 2x
    SYNCDELAY;
    OUTPKTEND = 0x82; // 3x
    SYNCDELAY;
    OUTPKTEND = 0x82; // 4x
    SYNCDELAY;
    EP2FIFOCFG = 0x11;                
    SYNCDELAY; 
 
    // IN EP6
    EP6FIFOCFG = 0x0D;                
    SYNCDELAY;
}