However, I need more communication bandwidth between the PC and FPGA. I implement a FX2LP controller to operate cy7c68013a chip, and communicate with Nios system that is shown as follow.
FX2LP is configured to Slave FIFO mode, and uses adapter to connect DE2-115.
The interface of FX2LP is 16-bit width, and can operate at 48 or 30Mhz. The NiosII system interface is 32-bit data bus, and operates at more than 100Mhz. The cyusb controller use a data combination logic to bridge them. In this case, FX2LP operates at 30Mhz because the wire of the adapter is too long. The EP2-OUT can read a 16-bit data in one clock cycle, and the bandwidth of the EP2-OUT is 60Mbyte/s(30Mhz*2bytes). The bandwidth of EP6-IN is limited by NiosII system interface. This system can write 2048 bytes data in 3553 clock cycles. The bandwidth of EP6-IN is about 17Mbyte/s if the data is moved by nios cpu.
The EP6-IN of FX2LP can be effectively wrote if the DMA is used to move the data. The cyusb controller can write 2048 bytes to EP6-IN in 2048 clock cycles if the data is moved by DMA. To improve the adapter or the FX2LP PCB module, the interface of FX2LP chip can operate at 48Mhz, and the access bandwidth can upgrade to 96Mbyte.
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