[Introduction]
SyntaxHighlighter中預設沒有提供,
a. Verilog
b. VHDL
c. TCL
這三種設計數位電路常用的語言,因此必須依照SyntaxHighlighter的框架,
編寫shBrushVerilog.js加入\syntaxhighlighter_3.0.83\scriptsscripts資料夾中。
SyntaxHighlighter色碼代號
- comments
- keyword
- string
- preprocessor
- variable
- value
- functions
- constants
- script
- color1
- color2
- color3
[shBrushVerilog.js]
剛開始可以使用shBrushCpp.js當作範本來修改,
兩個主要的工作,
a. 編輯shBrushVerilog.js。
b. 加入註冊shBrushVerilog.js的script加入到Blogger的範本中,即可使用。
/**
* Tun-Kai Yao
* tunkai.yao@gmail.com
*
* @ SyntaxHighlighter version
* 3.0.83 (July 02 2010)
*
* @copyright
* Copyright (C) 2004-2010 Alex Gorbatchev.
*
* @license
* Dual licensed under the MIT and GPL licenses.
*/
;(function()
{
// CommonJS
typeof(require) != 'undefined' ? SyntaxHighlighter = require('shCore').SyntaxHighlighter : null;
function Brush()
{
// 字集
// 資料型態
var datatypes = 'reg wire ' +
'integar unsigned ' +
'tri wand triand tri0 tri1 trireg supply0 supply1 ';
// 基本元件
var primitives = 'and nand or nor xor xnor ' +
'buf not ' +
'bufif0 bufif1 notif0 notif1 ' +
'pullup pulldown ' +
'pmos rpmos nmos rnmos ';
// 關鍵字
var keywords = 'module endmodule ' +
'input output inout ' +
'begin end ' +
'parameter defparam ' +
'assign deassign always initial genvar ' +
'forever repeat disable wait ' +
'function endfunction' +
'task endtask ' +
'generate endgenerate ' +
'specify endspecify ' +
'posedge negedge ' +
'if else for while ' +
'case casex casez endcase default ' +
//'include timescale ' +
//'ifdef endif ' +
'celldefine endcelldefine ' +
'attribute ' +
'specparam event' +
'fork join ';
// Tasks
var sysTasks = '$display $monitor $dumpall $dumpfile $dumpflush ' +
'$dumplimit $dumpoff $dumpon $dumpvars $fclose ' +
'$fdisplay $fopen $finish $fmonitor $fstrobe ' +
'$fwrite $fgetc $ungetc $fgets $fscanf $fread ' +
'$ftell $fseek $frewind $ferror $fflush $feof ' +
'$random $readmemb $readmemh $readmemx $signed ' +
'$stime $stop $strobe $time $unsigned $write';
// 著色
this.regexList = [
{ regex: SyntaxHighlighter.regexLib.singleLineCComments, css: 'comments' }, // one line comments
{ regex: SyntaxHighlighter.regexLib.multiLineCComments, css: 'comments' }, // multiline comments
{ regex: SyntaxHighlighter.regexLib.doubleQuotedString, css: 'string' }, // strings
{ regex: SyntaxHighlighter.regexLib.singleQuotedString, css: 'string' }, // strings
{ regex: /\b([\d]+(\.[\d]+)?|0x[a-f0-9]+)\b/gi, css: 'constants' }, // value
{ regex: /^ *#.*/gm, css: 'preprocessor' }, // #10
{ regex: /^ *`.*/gm, css: 'preprocessor' }, // `timescale
{ regex: new RegExp("[0-9]+['][bBoOdDhHeEfFtT][0-9a-fA-FzZxX_]+", 'g'), css: 'constants' },
{ regex: new RegExp(this.getKeywords(datatypes), 'gm'), css: 'color2 bold' },
{ regex: new RegExp(this.getKeywords(primitives), 'gm'), css: 'color3 bold' },
{ regex: new RegExp(this.getKeywords(sysTasks), 'gm'), css: 'functions bold' },
{ regex: new RegExp(this.getKeywords(keywords), 'gm'), css: 'keyword bold' }
];
};
Brush.prototype = new SyntaxHighlighter.Highlighter();
// 註冊 verilog 標籤
Brush.aliases = ['verilog'];
SyntaxHighlighter.brushes.Verilog = Brush;
// CommonJS
typeof(exports) != 'undefined' ? exports.Brush = Brush : null;
})();
[Verilog Example]
/* verilog
*/
`timescale 10/10
module rpa(
rpa_i_a,
rpa_i_b,
rpa_i_ci,
rpa_o_s,
rpa_o_co
);
input rpa_i_a;
input rpa_i_b;
input rpa_i_ci;
output rpa_o_s;
output rpa_o_co;
assign {rpa_o_co, rpa_o_s} = rpa_i_a + rpa_i_b + rpa_i_ci;
//test code
reg [15:0] testa;
wire [15:0] testb;
assign testa = 16'b0;
assign testb = 16'h0;
always@(posedge clk or negedge rst)
begin
if(!~rst) begin
end
else begin
end
end
endmodule