DE2-115 SDRAM Controller CAS=2

The SDRAM model of DE2-115 is IS42S16320 that can operate at 100Mhz~143Mhz. To operate at 143Mhz, CAS parameter is 3. At 100Mhz, CAS parameter is 2, and others of the sdram controller are shown as follow.

DE2-115 NiosII Lite by Qsys

To save the same steps, I use qsys to build a NiosII lite project for DE2-115. My other projects can base NiosII lite project, and add in other functions. The diagram of the NiosII lite is shown as follow.

The Qsys builder is freer than sopc builder. It could not create in quartus project, and can generate qsys`s synthesis file in selected path. The quartus project can find the qsys module when the quartus project adds in the *.qip that generated by qsys builder.

The qsys builder can show the example information of the port map that is shown as follow.

To add in *.qip file, the quartus project can find the generated synthesis file of the qsys builder.

After synthesizing and programing this project, the nios EDS can debug this project. In the compression file, I use a hello world program to verify this soc.

Download Link: Verification_SoC_Lite_v1.7z

Virtual JTAG access SRAM

In this approach, PC`s software can directly use Altera USB-Blaster to access the SRAM of the FPGA development board. It is a very good approach use to transfer small data. Because this usb access approach can`t meet my bandwidth requirement, I pause this project. I use FX2LP to get more communication bandwidth. I put source code of this project to this link.

I implement this approach in altera cycloneIII device, and the miatc3x development board is shown as follow.

Altera CycloneIII & Taiwan`s $10 coin

The front of the development board

The back of the development board

I implement this project when I am a newbie, and I don`t use SDC to constrain this design at the time. It maybe make the timing can`t met. The diagram of this project is shown as follow.

Altera USB-Blaster must use TCL to opetate, and TCL script can use tcl/tk to create a GUI. The operation flow of the GUI is shown as follow.

This GUI can read a image form PC`s disk, and uses Altera USB-Blaster to write sram of the FPGA board. After writing sram, the GUI can use usb-blaster to read sram of the FPGA board, and show the image data to the image plane of the GUI.

FX2LP (cy7c68013a) for Nios

DE2-115 of Terasic uses the ISP1362 full speed USB Host&OTG chip, and Terasic provides design examples for NiosII.

However, I need more communication bandwidth between the PC and FPGA. I implement a FX2LP controller to operate cy7c68013a chip, and communicate with Nios system that is shown as follow.

FX2LP is configured to Slave FIFO mode, and uses adapter to connect DE2-115.

The interface of FX2LP is 16-bit width, and can operate at 48 or 30Mhz. The NiosII system interface is 32-bit data bus, and operates at more than 100Mhz. The cyusb controller use a data combination logic to bridge them. In this case, FX2LP operates at 30Mhz because the wire of the adapter is too long. The EP2-OUT can read a 16-bit data in one clock cycle, and the bandwidth of the EP2-OUT is 60Mbyte/s(30Mhz*2bytes). The bandwidth of EP6-IN is limited by NiosII system interface. This system can write 2048 bytes data in 3553 clock cycles. The bandwidth of EP6-IN is about 17Mbyte/s if the data is moved by nios cpu.

The EP6-IN of FX2LP can be effectively wrote if the DMA is used to move the data. The cyusb controller can write 2048 bytes to EP6-IN in 2048 clock cycles if the data is moved by DMA. To improve the adapter or the FX2LP PCB module, the interface of FX2LP chip can operate at 48Mhz, and the access bandwidth can upgrade to 96Mbyte.

Qsys Builder of Altera QuartusII 10.1

I try to use qsys to rebuild my verification system that is shown as follow.

In qsys, some components are different form sopc builder. The Nor Flash(CFI) controller was replaced by Generic Tristate Controller. The altpll component doesn`t directly output clock, and the clock bridge component uses to output the clock of the sdram. The interface of the component can configure to directly export to outside of qsys.

Qsys has a new AvalonMM component is Avalon-MM Crossing Clock component. It uses the dual channel fifo to separate the different clock. In this case, I try to use it to replace the bus bridge 0, but the timingquest doesn`t met. I don`t understand what`s happen? The SDC file is generated by qsys. It means the design constrain is control by qsys. So, the bus bridge still use the Avalon-MM pipeline bridge.

This verification system uses the qsys to generate that can operate at 176Mhz in the DE2-115(Cyclone-IV).

DE2-115 開箱

[Introduction]
大概9月初就拿到DE2-115這個新玩具，忙到最近才有空拿出來，照幾張開箱照，給想買的同學參考。

[Article]

DE2-115外盒

這一次的外盒頗有設計感

DE2-115 實驗板

表面看來大致上與DE2-70相仿，但是仔細看有許多地方不盡相同，其實有不少的改變。最明顯的是GPIO已經被換成HSMC的介面，也有將JTAG chain加入，將可以串接FPGA，一起燒綠，並高速交換資料。

DE2-115 下層內容物

這一次友晶的配件多附贈一個紅外線的搖控器，這樣就不需要到處去尋覓合適的配件。

CycloneIV 與記憶體們

DE2-115改採用CycloneIV的Device，容量上有不少的增進，速度時脈也有提升，SDRAM也倍數增加到128MB(64MB*2)，但是可以注意到PCB的LAYOUT，兩顆SDRAM的位址與控制線都被接在一起，所以只能當作32bit的SDRAM來使用，要分該用應該很難了。 SRAM的部分，從SSRAM換成較好操作的2MB SRAM。Flash的部分LAYOUT也有修改，以往採用16-bit的資料線，現在改成8-bit，所以要注意一下位址線的用法不同。

GigaByte的Ethernet

Ethernet從常見的DM9000A，換成兩顆giga等級的Ethernet

電源

一改之前的linear的解決方案，改用National的解決方案，個人覺得還是Linear的方案比較簡潔。 這一次提供兩組JP，供使用者改變GPIO與HSMC的電壓準位，

側面

最後側面來一張

辛勞的DE2-70

滿是灰塵的DE2-70，但是想退休還早得很