Change the optimization option to disable when starting Modelsim

Find the modelsim.ini file in the install path, and Change "VoptFlow" parameter to false in the file.

[vsim]

; vopt flow

; Set to turn on automatic optimization of a design.

; Default is on

VoptFlow = 0

MATLAB save neural network object to file

it is a easy operation that saves the neural network object to MAT-file in the MATLAB, but the problem is how to load the neural network object from MAT-file.

save the neural network object

    save('./dat/bpnn_00.mat', 'bpnn'); 
    %    | file name      |  nn obj | // it`s easy.

load the neural network object

    newData1 = load('-mat', './dat/bpnn_00.mat');
    
    % transfer variable format
    vars = fieldnames(newData1);
    for i = 1:length(vars)
        assignin('base', vars{i}, newData1.(vars{i}));
    end

MATLAB get 'bpnn' of the neural network object, but the neural network can`t simulate. I don`t know why the neural network object can`t directly simulate.

    nnResult = sim(bpnn, nnInput); % nnResult is error value

I add a 'getx' function to program, and 'nnResult' of the neural network is correct value. Why?

    nnWB = getx(bpnn); % <-- why? 
    nnResult = sim(bpnn, nnInput); % nnResult is correct value

It maybe the weight and bias value don`t put to the variable of the neural network tool when MATLAB load the MAT-file.

STM32F103 Timer - base operation

Using Timer2 of STM32F103 to trigger Interrupt every 1us, and the initiation is shown as follow.

void init_timer(void)
{
    TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;  
    NVIC_InitTypeDef NVIC_InitStructure;

    RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);
 
    TIM_TimeBaseStructure.TIM_Period = 0xA;     // Counter 12 = 1Mhz = 1us        
    TIM_TimeBaseStructure.TIM_Prescaler = 0x5;  // 72Mhz/6 = 12Mhz       
    TIM_TimeBaseStructure.TIM_ClockDivision = 0x0;    
    TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;  
    TIM_TimeBaseStructure.TIM_RepetitionCounter = 0x0000;
    TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);
 
    NVIC_PriorityGroupConfig(NVIC_PriorityGroup_0);
    NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQn;
    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
    NVIC_Init(&NVIC_InitStructure);
 
    TIM_ClearFlag(TIM2, TIM_FLAG_Update);
    TIM_ITConfig(TIM2, TIM_IT_Update, ENABLE);
    TIM_Cmd(TIM2, ENABLE);
}

The program counter goes into TIM2_IRQHandler function when the timer2 trigger interrupt flag.

void TIM2_IRQHandler(void)
{
    // Timer2 Interrupt Handler
}

DE2-115 SDRAM Controller CAS=2

The SDRAM model of DE2-115 is IS42S16320 that can operate at 100Mhz~143Mhz. To operate at 143Mhz, CAS parameter is 3. At 100Mhz, CAS parameter is 2, and others of the sdram controller are shown as follow.

DE2-115 NiosII Lite by Qsys

To save the same steps, I use qsys to build a NiosII lite project for DE2-115. My other projects can base NiosII lite project, and add in other functions. The diagram of the NiosII lite is shown as follow.

The Qsys builder is freer than sopc builder. It could not create in quartus project, and can generate qsys`s synthesis file in selected path. The quartus project can find the qsys module when the quartus project adds in the *.qip that generated by qsys builder.

The qsys builder can show the example information of the port map that is shown as follow.

To add in *.qip file, the quartus project can find the generated synthesis file of the qsys builder.

After synthesizing and programing this project, the nios EDS can debug this project. In the compression file, I use a hello world program to verify this soc.

Download Link: Verification_SoC_Lite_v1.7z

Virtual JTAG access SRAM

In this approach, PC`s software can directly use Altera USB-Blaster to access the SRAM of the FPGA development board. It is a very good approach use to transfer small data. Because this usb access approach can`t meet my bandwidth requirement, I pause this project. I use FX2LP to get more communication bandwidth. I put source code of this project to this link.

I implement this approach in altera cycloneIII device, and the miatc3x development board is shown as follow.

Altera CycloneIII & Taiwan`s $10 coin

The front of the development board

The back of the development board

I implement this project when I am a newbie, and I don`t use SDC to constrain this design at the time. It maybe make the timing can`t met. The diagram of this project is shown as follow.

Altera USB-Blaster must use TCL to opetate, and TCL script can use tcl/tk to create a GUI. The operation flow of the GUI is shown as follow.

This GUI can read a image form PC`s disk, and uses Altera USB-Blaster to write sram of the FPGA board. After writing sram, the GUI can use usb-blaster to read sram of the FPGA board, and show the image data to the image plane of the GUI.

FX2LP (cy7c68013a) for Nios

DE2-115 of Terasic uses the ISP1362 full speed USB Host&OTG chip, and Terasic provides design examples for NiosII.

However, I need more communication bandwidth between the PC and FPGA. I implement a FX2LP controller to operate cy7c68013a chip, and communicate with Nios system that is shown as follow.

FX2LP is configured to Slave FIFO mode, and uses adapter to connect DE2-115.

The interface of FX2LP is 16-bit width, and can operate at 48 or 30Mhz. The NiosII system interface is 32-bit data bus, and operates at more than 100Mhz. The cyusb controller use a data combination logic to bridge them. In this case, FX2LP operates at 30Mhz because the wire of the adapter is too long. The EP2-OUT can read a 16-bit data in one clock cycle, and the bandwidth of the EP2-OUT is 60Mbyte/s(30Mhz*2bytes). The bandwidth of EP6-IN is limited by NiosII system interface. This system can write 2048 bytes data in 3553 clock cycles. The bandwidth of EP6-IN is about 17Mbyte/s if the data is moved by nios cpu.

The EP6-IN of FX2LP can be effectively wrote if the DMA is used to move the data. The cyusb controller can write 2048 bytes to EP6-IN in 2048 clock cycles if the data is moved by DMA. To improve the adapter or the FX2LP PCB module, the interface of FX2LP chip can operate at 48Mhz, and the access bandwidth can upgrade to 96Mbyte.

Qsys Builder of Altera QuartusII 10.1

I try to use qsys to rebuild my verification system that is shown as follow.

In qsys, some components are different form sopc builder. The Nor Flash(CFI) controller was replaced by Generic Tristate Controller. The altpll component doesn`t directly output clock, and the clock bridge component uses to output the clock of the sdram. The interface of the component can configure to directly export to outside of qsys.

Qsys has a new AvalonMM component is Avalon-MM Crossing Clock component. It uses the dual channel fifo to separate the different clock. In this case, I try to use it to replace the bus bridge 0, but the timingquest doesn`t met. I don`t understand what`s happen? The SDC file is generated by qsys. It means the design constrain is control by qsys. So, the bus bridge still use the Avalon-MM pipeline bridge.

This verification system uses the qsys to generate that can operate at 176Mhz in the DE2-115(Cyclone-IV).

FX2LP Slave FIFO Mode (cy7c68013a)

FX2LP Slave FIFO Mode Firmware

The 8051 of the FX2LP only uses to initial the configuration register, and the configuration of the endpoint is shown as follow:


EP2 OUT
4x Buffer
512 Bytes Packet
Auto-OUT

EP6 IN
4x Buffer
512 Bytes Packet
Auto-IN

void TD_Init( void )
{ 
    CPUCS = 0x12;                       // cpu freq. = 24Mhz
    SYNCDELAY; 
 
    IFCONFIG = 0xA3;                    // ifclk freq. = 30Mhz
    SYNCDELAY;

    PINFLAGSAB = 0x88;   // FLAGA - EP2 EF
    SYNCDELAY;
    PINFLAGSCD = 0xEE;   // FLAGD - EP6 FF
    SYNCDELAY;

    PORTACFG |= 0x80;
    SYNCDELAY;

    FIFOPINPOLAR = 0x3F;                // setting all interface to high active
    SYNCDELAY;
      
    EP4CFG = 0x02; // Clear Valid                    
    SYNCDELAY;
    EP8CFG = 0x02; // Clear Valid
    SYNCDELAY;                   
    EP2CFG = 0xA0;// OUT 512 4x
    SYNCDELAY;
    EP6CFG = 0xE0;// IN  512 4x
    SYNCDELAY;
     
    // Clear FIFO
    FIFORESET = 0x80;             // activate NAK-ALL to avoid race conditions
    SYNCDELAY;                    
    FIFORESET = 0x02;             // reset, FIFO 2
    SYNCDELAY;                    // 
    FIFORESET = 0x04;             // reset, FIFO 4
    SYNCDELAY;                    // 
    FIFORESET = 0x06;             // reset, FIFO 6
    SYNCDELAY;                    // 
    FIFORESET = 0x08;             // reset, FIFO 8
    SYNCDELAY;                    // 
    FIFORESET = 0x00;             // deactivate NAK-ALL
    SYNCDELAY;

    // OUT EP2
    EP2FIFOCFG = 0x01; // AUTOOUT = 0             
    SYNCDELAY;
    OUTPKTEND = 0x82; // 1x
    SYNCDELAY;
    OUTPKTEND = 0x82; // 2x
    SYNCDELAY;
    OUTPKTEND = 0x82; // 3x
    SYNCDELAY;
    OUTPKTEND = 0x82; // 4x
    SYNCDELAY;
    EP2FIFOCFG = 0x11;                
    SYNCDELAY; 
 
    // IN EP6
    EP6FIFOCFG = 0x0D;                
    SYNCDELAY;
}