Change the optimization option to disable when starting Modelsim

Find the modelsim.ini file in the install path, and Change "VoptFlow" parameter to false in the file.

[vsim]

; vopt flow

; Set to turn on automatic optimization of a design.

; Default is on

VoptFlow = 0

MATLAB save neural network object to file

it is a easy operation that saves the neural network object to MAT-file in the MATLAB, but the problem is how to load the neural network object from MAT-file.

save the neural network object

    save('./dat/bpnn_00.mat', 'bpnn'); 
    %    | file name      |  nn obj | // it`s easy.

load the neural network object

    newData1 = load('-mat', './dat/bpnn_00.mat');
    
    % transfer variable format
    vars = fieldnames(newData1);
    for i = 1:length(vars)
        assignin('base', vars{i}, newData1.(vars{i}));
    end

MATLAB get 'bpnn' of the neural network object, but the neural network can`t simulate. I don`t know why the neural network object can`t directly simulate.

    nnResult = sim(bpnn, nnInput); % nnResult is error value

I add a 'getx' function to program, and 'nnResult' of the neural network is correct value. Why?

    nnWB = getx(bpnn); % <-- why? 
    nnResult = sim(bpnn, nnInput); % nnResult is correct value

It maybe the weight and bias value don`t put to the variable of the neural network tool when MATLAB load the MAT-file.

STM32F103 Timer - base operation

Using Timer2 of STM32F103 to trigger Interrupt every 1us, and the initiation is shown as follow.

void init_timer(void)
{
    TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;  
    NVIC_InitTypeDef NVIC_InitStructure;

    RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);
 
    TIM_TimeBaseStructure.TIM_Period = 0xA;     // Counter 12 = 1Mhz = 1us        
    TIM_TimeBaseStructure.TIM_Prescaler = 0x5;  // 72Mhz/6 = 12Mhz       
    TIM_TimeBaseStructure.TIM_ClockDivision = 0x0;    
    TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;  
    TIM_TimeBaseStructure.TIM_RepetitionCounter = 0x0000;
    TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);
 
    NVIC_PriorityGroupConfig(NVIC_PriorityGroup_0);
    NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQn;
    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
    NVIC_Init(&NVIC_InitStructure);
 
    TIM_ClearFlag(TIM2, TIM_FLAG_Update);
    TIM_ITConfig(TIM2, TIM_IT_Update, ENABLE);
    TIM_Cmd(TIM2, ENABLE);
}

The program counter goes into TIM2_IRQHandler function when the timer2 trigger interrupt flag.

void TIM2_IRQHandler(void)
{
    // Timer2 Interrupt Handler
}

DE2-115 SDRAM Controller CAS=2

The SDRAM model of DE2-115 is IS42S16320 that can operate at 100Mhz~143Mhz. To operate at 143Mhz, CAS parameter is 3. At 100Mhz, CAS parameter is 2, and others of the sdram controller are shown as follow.

DE2-115 NiosII Lite by Qsys

To save the same steps, I use qsys to build a NiosII lite project for DE2-115. My other projects can base NiosII lite project, and add in other functions. The diagram of the NiosII lite is shown as follow.

The Qsys builder is freer than sopc builder. It could not create in quartus project, and can generate qsys`s synthesis file in selected path. The quartus project can find the qsys module when the quartus project adds in the *.qip that generated by qsys builder.

The qsys builder can show the example information of the port map that is shown as follow.

To add in *.qip file, the quartus project can find the generated synthesis file of the qsys builder.

After synthesizing and programing this project, the nios EDS can debug this project. In the compression file, I use a hello world program to verify this soc.

Download Link: Verification_SoC_Lite_v1.7z

Virtual JTAG access SRAM

In this approach, PC`s software can directly use Altera USB-Blaster to access the SRAM of the FPGA development board. It is a very good approach use to transfer small data. Because this usb access approach can`t meet my bandwidth requirement, I pause this project. I use FX2LP to get more communication bandwidth. I put source code of this project to this link.

I implement this approach in altera cycloneIII device, and the miatc3x development board is shown as follow.

Altera CycloneIII & Taiwan`s $10 coin

The front of the development board

The back of the development board

I implement this project when I am a newbie, and I don`t use SDC to constrain this design at the time. It maybe make the timing can`t met. The diagram of this project is shown as follow.

Altera USB-Blaster must use TCL to opetate, and TCL script can use tcl/tk to create a GUI. The operation flow of the GUI is shown as follow.

This GUI can read a image form PC`s disk, and uses Altera USB-Blaster to write sram of the FPGA board. After writing sram, the GUI can use usb-blaster to read sram of the FPGA board, and show the image data to the image plane of the GUI.

FX2LP (cy7c68013a) for Nios

DE2-115 of Terasic uses the ISP1362 full speed USB Host&OTG chip, and Terasic provides design examples for NiosII.

However, I need more communication bandwidth between the PC and FPGA. I implement a FX2LP controller to operate cy7c68013a chip, and communicate with Nios system that is shown as follow.

FX2LP is configured to Slave FIFO mode, and uses adapter to connect DE2-115.

The interface of FX2LP is 16-bit width, and can operate at 48 or 30Mhz. The NiosII system interface is 32-bit data bus, and operates at more than 100Mhz. The cyusb controller use a data combination logic to bridge them. In this case, FX2LP operates at 30Mhz because the wire of the adapter is too long. The EP2-OUT can read a 16-bit data in one clock cycle, and the bandwidth of the EP2-OUT is 60Mbyte/s(30Mhz*2bytes). The bandwidth of EP6-IN is limited by NiosII system interface. This system can write 2048 bytes data in 3553 clock cycles. The bandwidth of EP6-IN is about 17Mbyte/s if the data is moved by nios cpu.

The EP6-IN of FX2LP can be effectively wrote if the DMA is used to move the data. The cyusb controller can write 2048 bytes to EP6-IN in 2048 clock cycles if the data is moved by DMA. To improve the adapter or the FX2LP PCB module, the interface of FX2LP chip can operate at 48Mhz, and the access bandwidth can upgrade to 96Mbyte.

Qsys Builder of Altera QuartusII 10.1

I try to use qsys to rebuild my verification system that is shown as follow.

In qsys, some components are different form sopc builder. The Nor Flash(CFI) controller was replaced by Generic Tristate Controller. The altpll component doesn`t directly output clock, and the clock bridge component uses to output the clock of the sdram. The interface of the component can configure to directly export to outside of qsys.

Qsys has a new AvalonMM component is Avalon-MM Crossing Clock component. It uses the dual channel fifo to separate the different clock. In this case, I try to use it to replace the bus bridge 0, but the timingquest doesn`t met. I don`t understand what`s happen? The SDC file is generated by qsys. It means the design constrain is control by qsys. So, the bus bridge still use the Avalon-MM pipeline bridge.

This verification system uses the qsys to generate that can operate at 176Mhz in the DE2-115(Cyclone-IV).

FX2LP Slave FIFO Mode (cy7c68013a)

FX2LP Slave FIFO Mode Firmware

The 8051 of the FX2LP only uses to initial the configuration register, and the configuration of the endpoint is shown as follow:


EP2 OUT
4x Buffer
512 Bytes Packet
Auto-OUT

EP6 IN
4x Buffer
512 Bytes Packet
Auto-IN

void TD_Init( void )
{ 
    CPUCS = 0x12;                       // cpu freq. = 24Mhz
    SYNCDELAY; 
 
    IFCONFIG = 0xA3;                    // ifclk freq. = 30Mhz
    SYNCDELAY;

    PINFLAGSAB = 0x88;   // FLAGA - EP2 EF
    SYNCDELAY;
    PINFLAGSCD = 0xEE;   // FLAGD - EP6 FF
    SYNCDELAY;

    PORTACFG |= 0x80;
    SYNCDELAY;

    FIFOPINPOLAR = 0x3F;                // setting all interface to high active
    SYNCDELAY;
      
    EP4CFG = 0x02; // Clear Valid                    
    SYNCDELAY;
    EP8CFG = 0x02; // Clear Valid
    SYNCDELAY;                   
    EP2CFG = 0xA0;// OUT 512 4x
    SYNCDELAY;
    EP6CFG = 0xE0;// IN  512 4x
    SYNCDELAY;
     
    // Clear FIFO
    FIFORESET = 0x80;             // activate NAK-ALL to avoid race conditions
    SYNCDELAY;                    
    FIFORESET = 0x02;             // reset, FIFO 2
    SYNCDELAY;                    // 
    FIFORESET = 0x04;             // reset, FIFO 4
    SYNCDELAY;                    // 
    FIFORESET = 0x06;             // reset, FIFO 6
    SYNCDELAY;                    // 
    FIFORESET = 0x08;             // reset, FIFO 8
    SYNCDELAY;                    // 
    FIFORESET = 0x00;             // deactivate NAK-ALL
    SYNCDELAY;

    // OUT EP2
    EP2FIFOCFG = 0x01; // AUTOOUT = 0             
    SYNCDELAY;
    OUTPKTEND = 0x82; // 1x
    SYNCDELAY;
    OUTPKTEND = 0x82; // 2x
    SYNCDELAY;
    OUTPKTEND = 0x82; // 3x
    SYNCDELAY;
    OUTPKTEND = 0x82; // 4x
    SYNCDELAY;
    EP2FIFOCFG = 0x11;                
    SYNCDELAY; 
 
    // IN EP6
    EP6FIFOCFG = 0x0D;                
    SYNCDELAY;
}

Asus F8sp安裝Windows7 x64

Asus是在驅動程式上面非常不用心的公司，
驅動程式鮮少在更新，而且散成一團，每次都要一個一個安裝(哀...雖然我知道驅動都是供應商寫的..但還是希望ATK合起來)，
所以每當在新作業系統快出的曖昧期，買到它的筆電真的很吐血，

Windows7都出多久了F8sp驅動程式連動都沒動，
偏偏比較新的F8vr有win7x64的驅動(幾乎一樣的晶片跟組件...這...資料庫關聯性真的很差)，

不過說真的幹嘛手賤，要安裝windows7 x64，好好用xp就天下太平，不是嗎? XD
剛開始有點怕怕滴..
怕有些驅動程式會互相衝突，畢竟是自己到處搜刮來的，不是Asus驗證過的驅動，
好家在, 安裝完沒啥大問題，不過有幾個注意事項；

1. Microsoft update裡的驅動有三個不要安裝
    a. ATI顯示驅動
    b. ITE紅外線驅動
    c. Ricoh xD讀卡機驅動

2. Microsoft update裡面需要安裝的驅動
    a. Realtek Ethernet驅動
    b. AuthenTec指紋Sensor驅動
    c. Motorola modem驅動

3. 以下需要下載安裝的驅動
    a. 怨念超深ATK系列
- AGFNEX_WIN7_32_WIN7_64_1000008
- ATK_Hotkey_Win7_32_64_100053
- ATKDrv_V104321575_Win7_64
- ATKOSD2_WIN7_32_WIN7_64_700006

    b. 非常無言的無線網路開關驅動，做個硬體開關會死嗎?
- Wireless_Console_Win7_32_64_2010
  
    c. 花俏不實用的電源管理
- Power4Gear_Hybrid_WIN7_64_110019
  
    d. 鍵盤相關驅動?
- KBFilter_WIN7_64_1003
    
    e. 觸控板驅動
- Synaptics_v14_0_3_C_XP64_Vista64_Win7-64_Signed_default
    
    f. AMD HD3650驅動
- AMD官方網站下載最新版本

    g. Realtek驅動
- High Definition Audio Codecs
- Realtek PCIe GBE Family Controller


    g. ITE 紅外線接收器驅動(千萬別亂裝.. 只有這一版能夠真正驅動)
- ITE_Romote_VT


    h. Ricoh讀卡機驅動
- CardReader_Ricoh_WIN7_32_WIN7_64_36202


     i. CAMERA驅動(注意一下! Asus F8sp的供料廠商有兩間.. 所以不一定是D-MAX)
- Camera_D-MAX_Win7_32_64_721701
      
    j. TPM信任模組驅動
- TPM_Infineon_WIN7_64_36


    k. 藍芽驅動(使用Microsofe內建)


安裝Windows7 64後的效能評等

ATI HD3650 1GB的桌面效能這麼低弱? 呵

安裝完成後其實發現很多驅動還是x32的驅動，不過現階段先不管這麼多，以後有出在做更換。

Altera FTP的隱藏目錄

鑑於最近
Altera_installer_rev2
莫名其妙都不會動，實在太＠＃＄＠＃＄

只好再把以前的技倆搬出來，用ftp多線程下載(altera: 哭哭)
ftp://ftp.altera.com/outgoing/release/

裡面有所有版本的Altera軟體

C語言讀寫BMP影像檔

[Introduction]
撰寫視窗軟體時應該是沒有如此的煩惱，因為bcb, vc++都有提供視覺化元件可以使用，但是對於開發演算法以及產生test pattern時根本不需要圖形化介面，或者是嵌入式系統在開發時需要使用semihosting輸出影像時，這時要開圖檔或者寫圖檔都是件麻煩事。而bmp是一個最簡單的泛用圖檔格式，但是又不須像raw一樣，需要設定長寬大小，只要點兩下馬上看得到結果。對於嵌入式系統或者vlsi相關的設計，有很大的幫助。因此這邊簡單寫一個讀寫bmp的函式。

[Article]
BMP檔案格式，由bmpheader與image array兩個部份組成。
bmp header通常長度為58byte，所以也可以值些忽略前面的部份，讀取影像的資料，但是為了寫回電腦時還是一樣是bmp檔，所以還是需要把header記下來，先宣告一個結構(struct)來存放header資料，

typedef struct _lbheader{
    unsigned short identifier;      // 0x0000
    unsigned int filesize;          // 0x0002
    unsigned int reserved;          // 0x0006
    unsigned int bitmap_dataoffset; // 0x000A
    unsigned int bitmap_headersize; // 0x000E
    unsigned int width;             // 0x0012
    unsigned int height;            // 0x0016
    unsigned short planes;          // 0x001A
    unsigned short bits_perpixel;   // 0x001C
    unsigned int compression;       // 0x001E
    unsigned int bitmap_datasize;   // 0x0022
    unsigned int hresolution;       // 0x0026
    unsigned int vresolution;       // 0x002A
    unsigned int usedcolors;        // 0x002E
    unsigned int importantcolors;   // 0x0032
    unsigned int palette;           // 0x0036
} __attribute__((packed,aligned(1))) lbheader;

記住gcc有資料格式對齊的考量，為了到時後讀檔方便，所以加入__attribute__((packed,aligned(1)))，強制gcc把結構作緊密排列，這樣是為了到時候讀取資料時可以直接使用指標來擺放資料，就不需要一筆一筆去指定資料。

lbheader hbmp;
unsigned char* ptr;
ptr = (unsigned char *)&hbmp;
fread(ptr, sizeof(unsigned char), sizeof(lbheader), fp);

像這樣開始讀取檔案的58byte，直接使用unsigned char型態指標從結構開始位址開始寫入，數值就會按照位置擺入結構中。
讀完header後，取出width與height，由於一個pixel有rgb三個pixel，算影像大小的公式為width*height*3，再與(filesize-bitmap_dataoffset)比較看看是否相等，判斷大小是否有算錯，
下面是讀取bmp的函式

int readbmp(char* filename, lbheader& hbmp, int mode, unsigned char* buffer)
{
    FILE* ifp;
    char c[128];
    unsigned char* ptr;

    sprintf(c, "./result/%s.bmp", filename);
    ifp = fopen(c, "rb");
    if(ifp==NULL){
        printf("readbmp: file open error\n");
        return -1;
    }

    ptr = (unsigned char *)&hbmp;
    fread(ptr, sizeof(unsigned char), sizeof(lbheader), ifp);

    if(mode==1){
        fread(buffer, sizeof(unsigned char), (hbmp.width*hbmp.height*3), ifp);
    }
    else{
        fclose(ifp);
        return (hbmp.width*hbmp.height*3);
    }

    fclose(ifp);
    return 1;
}

要讀取影像時要先知道影像大小，以便宣告足夠的記憶體空間，所以要呼叫兩次readbmp()，一次先取到header，第二次才真的取影像資料，

// 先宣告指標與結構
unsigned char* bimage;
lbheader bmpinfo; 
// 取得適當大小的陣列    
bimage = (unsigned char *)malloc(sizeof(unsigned char)*readbmp("2", bmpinfo, 0, bimage));
// 讀取影像    
readbmp("2", bmpinfo, 1, bimage);

寫入bmp的function。

int writebmp(char* filename, lbheader hbmp, unsigned char* buffer)
{
    FILE* ofp;
    char c[128];
    unsigned char* ptr;

    sprintf(c, "./result/%s.bmp", filename);
    ofp = fopen(c, "wb");
    if(ofp==NULL){
        printf("writebmp: file open error\n");
        return -1;
    }

    ptr = (unsigned char *)&hbmp;
    fwrite(ptr, sizeof(unsigned char), sizeof(lbheader), ofp);
    fwrite(buffer, sizeof(unsigned char), (hbmp.width*hbmp.height*3), ofp);

    fclose(ofp);
    return 1;
}

但是要注意一點，BMP擺放影像是上下顛倒所以要記得將影像轉回來，不然存出來的圖會是顛倒的。

DE2-115 開箱

[Introduction]
大概9月初就拿到DE2-115這個新玩具，忙到最近才有空拿出來，照幾張開箱照，給想買的同學參考。

[Article]

DE2-115外盒

這一次的外盒頗有設計感

DE2-115 實驗板

表面看來大致上與DE2-70相仿，但是仔細看有許多地方不盡相同，其實有不少的改變。最明顯的是GPIO已經被換成HSMC的介面，也有將JTAG chain加入，將可以串接FPGA，一起燒綠，並高速交換資料。

DE2-115 下層內容物

這一次友晶的配件多附贈一個紅外線的搖控器，這樣就不需要到處去尋覓合適的配件。

CycloneIV 與記憶體們

DE2-115改採用CycloneIV的Device，容量上有不少的增進，速度時脈也有提升，SDRAM也倍數增加到128MB(64MB*2)，但是可以注意到PCB的LAYOUT，兩顆SDRAM的位址與控制線都被接在一起，所以只能當作32bit的SDRAM來使用，要分該用應該很難了。 SRAM的部分，從SSRAM換成較好操作的2MB SRAM。Flash的部分LAYOUT也有修改，以往採用16-bit的資料線，現在改成8-bit，所以要注意一下位址線的用法不同。

GigaByte的Ethernet

Ethernet從常見的DM9000A，換成兩顆giga等級的Ethernet

電源

一改之前的linear的解決方案，改用National的解決方案，個人覺得還是Linear的方案比較簡潔。 這一次提供兩組JP，供使用者改變GPIO與HSMC的電壓準位，

側面

最後側面來一張

辛勞的DE2-70

滿是灰塵的DE2-70，但是想退休還早得很

SyntaxHighlighter加入TCL Brush

[Introduction]
續"SyntaxHighlighter加入Verilog Brush"，
增加TCL Brush。

[shBrushTcl.js]
Download

[TCL Example]

#** OpenPPM -- opens and reads a PPM file
#**
proc OpenPPM {} {
    global readimg
    
    set types { {{PPM Files} {.ppm}} {{All Files} * }}
    set fname [tk_getOpenFile -defaultextension ".ppm" -filetypes $types]
    if {$fname == ""} return
    #::img::current config -file $fname
    $readimg config -file $fname
}

SyntaxHighlighter中加入Verilog Brush

[Introduction]
SyntaxHighlighter中預設沒有提供，
a. Verilog
b. VHDL
c. TCL
這三種設計數位電路常用的語言，因此必須依照SyntaxHighlighter的框架，
編寫shBrushVerilog.js加入\syntaxhighlighter_3.0.83\scriptsscripts資料夾中。 

SyntaxHighlighter色碼代號

• comments 
• keyword 
• string 
• preprocessor 
• variable 
• value 
• functions 
• constants 
• script 
• color1 
• color2 
• color3

 
[shBrushVerilog.js]
 剛開始可以使用shBrushCpp.js當作範本來修改，
兩個主要的工作，
a. 編輯shBrushVerilog.js。
b. 加入註冊shBrushVerilog.js的script加入到Blogger的範本中，即可使用。

/**
 * Tun-Kai Yao
 * tunkai.yao@gmail.com
 *
 * @ SyntaxHighlighter version
 * 3.0.83 (July 02 2010)
 * 
 * @copyright
 * Copyright (C) 2004-2010 Alex Gorbatchev.
 *
 * @license
 * Dual licensed under the MIT and GPL licenses.
 */
;(function()
{
    // CommonJS
    typeof(require) != 'undefined' ? SyntaxHighlighter = require('shCore').SyntaxHighlighter : null;

    function Brush()
    {
        // 字集
        // 資料型態    
        var datatypes = 'reg wire ' +
                        'integar unsigned ' +
                        'tri wand triand tri0 tri1 trireg supply0 supply1 ';
                        
        // 基本元件
        var primitives = 'and nand or nor xor xnor ' +
                         'buf not ' +
                         'bufif0 bufif1 notif0 notif1 ' +
                         'pullup pulldown ' +
                         'pmos rpmos nmos rnmos ';

        // 關鍵字
        var keywords =  'module endmodule ' +                        
                        'input output inout ' +
                        'begin end ' +
                        'parameter defparam ' +
                        'assign deassign always initial genvar ' +
                        'forever repeat disable wait ' +
                        'function endfunction' +
                        'task endtask ' +
                        'generate endgenerate ' +
                        'specify endspecify ' +
                        'posedge negedge ' +
                        'if else for while ' +
                        'case casex casez endcase default ' +
                        //'include timescale ' +
                        //'ifdef endif ' +
                        'celldefine endcelldefine ' +
                        'attribute ' +
                        'specparam  event' +
                        'fork join ';
        
        // Tasks
        var sysTasks = '$display $monitor $dumpall $dumpfile $dumpflush ' +
                       '$dumplimit $dumpoff $dumpon $dumpvars $fclose ' +
                       '$fdisplay $fopen $finish $fmonitor $fstrobe ' +
                       '$fwrite $fgetc $ungetc $fgets $fscanf $fread ' +
                       '$ftell $fseek $frewind $ferror $fflush $feof ' +
                       '$random $readmemb $readmemh $readmemx $signed ' +
                       '$stime $stop $strobe $time $unsigned $write';

        // 著色
        this.regexList = [
            { regex: SyntaxHighlighter.regexLib.singleLineCComments,    css: 'comments' },              // one line comments
            { regex: SyntaxHighlighter.regexLib.multiLineCComments,     css: 'comments' },              // multiline comments
            { regex: SyntaxHighlighter.regexLib.doubleQuotedString,     css: 'string' },                // strings
            { regex: SyntaxHighlighter.regexLib.singleQuotedString,     css: 'string' },                // strings
            { regex: /\b([\d]+(\.[\d]+)?|0x[a-f0-9]+)\b/gi,             css: 'constants' },             // value
            { regex: /^ *#.*/gm,                                        css: 'preprocessor' },          // #10
            { regex: /^ *`.*/gm,                                        css: 'preprocessor'  },         // `timescale
            { regex: new RegExp("[0-9]+['][bBoOdDhHeEfFtT][0-9a-fA-FzZxX_]+", 'g'), css: 'constants' },
            { regex: new RegExp(this.getKeywords(datatypes), 'gm'),     css: 'color2 bold' },
            { regex: new RegExp(this.getKeywords(primitives), 'gm'),    css: 'color3 bold' },
            { regex: new RegExp(this.getKeywords(sysTasks), 'gm'),      css: 'functions bold' },
            { regex: new RegExp(this.getKeywords(keywords), 'gm'),      css: 'keyword bold' }
            ];
    };

    Brush.prototype = new SyntaxHighlighter.Highlighter();
    // 註冊 verilog 標籤
    Brush.aliases = ['verilog']; 
    SyntaxHighlighter.brushes.Verilog = Brush;

    // CommonJS
    typeof(exports) != 'undefined' ? exports.Brush = Brush : null;
})();

[Verilog Example]

/* verilog
 */
`timescale 10/10

module rpa(
    rpa_i_a,
    rpa_i_b,
    rpa_i_ci,
    rpa_o_s,
    rpa_o_co
);

    input  rpa_i_a;
    input  rpa_i_b;
    input  rpa_i_ci;
    output rpa_o_s;
    output rpa_o_co;

    assign {rpa_o_co, rpa_o_s} = rpa_i_a + rpa_i_b + rpa_i_ci;
    
    //test code
    reg [15:0] testa;
    wire [15:0] testb;
    assign testa = 16'b0;
    assign testb = 16'h0;

    always@(posedge clk or negedge rst)
    begin
        if(!~rst) begin
        
        end
        else begin

        end
    end


endmodule

Blogger加入SyntaxHighlighter樣式

Source Link: SyntaxHighlighter


(一) 修改Blogger樣式
1.下載SyntaxHighlighter樣式, 下載連結 (版本 3.0.83)
2. 將SyntaxHighlighter解壓，並放入webserver (或者使用作者所提供的空間)
3. 加入javascript與css到Blogger範本 <b:skin> 標籤之前


4. Blogger範本</body>前呼叫

5. 文章中插入程式碼的呼叫方式
    a.

<pre class="brush: js">

    /**

     * SyntaxHighlighter

     */

    function foo()

    {

        if (counter <= 10)

            return;

        // it works!

    }

</pre>

   
    b.

<script type="syntaxhighlighter" class="brush: js"><![CDATA[

  /**

   * SyntaxHighlighter

   */

  function foo()

  {

      if (counter <= 10)

          return;

      // it works!

  }

]]></script>

測試

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